The present invention relates to interconnects of integrated circuits and semiconductor chip packages.
An integrated circuit (IC) die is a small device formed on a semiconductor wafer, such as a silicon wafer. Such a die is typically cut from the wafer and attached to a substrate for interconnect redistribution. Bond pads on the die are then electrically connected to the leads on the carrier via wire bonding. The die and the bonding wires are then encapsulated with a molding compound such that a package is formed.
Typically, the leads encapsulated in the package are redistributed in a network of conductors within the carrier and end in an array of terminal points outside the package. Manufacturers have been stacking two or more die within a single package. Such devices are sometimes referred to as stacked multichip packages.
One stacked multichip package is generally illustrated in FIG. 1. In this configuration a first die 11 is mounted on a substrate 10. A second die 12 may then be adhesively secured to the top surface of the first die 11 thereby creating a stacked die configuration. The second die 12 partially overlaps with the first die 11 when viewed from the above. Bonding wires 16 and 18 are then used to electrically connect the first die 11 and the second die 12 to the respective bond fingers on the substrate 10 using conventional wire bonder. An encapsulant material 20 is molded over the substrate 10 to provide an encapsulant cap.
As known in the art, a stand-off stitch bonding process typically comprises placing a flat-topped bump on an active integrated circuit (IC) pad such as an aluminum pad, and then reverse bonding from the substrate or package back to the flat-topped ball bump. However, it is difficult to form the wire bond 18 on the bond pads of the second die 12 adjacent to the overhanging side edge 12a. The stress incurred by the wire bonder may cause peeling between the first die 11 and the second die 12 and reduce the production yield.